VX6854LC datasheet(63/114 Pages) STMICROELECTRONICS

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VX6854LC

Video timing

Note:

op_sys_clk_div should equal vt_sys_clk_div and op_pix_clk_div should equal

vt_pix_clk_div for these examples.

6.2.4

Derating

To provide a wide range of data rate reduction options the full image scaler is able to reduce

the data and therefore data rates in both the horizontal and vertical directions. In the

VX6854LC this is achieved by the use of a FIFO between video timing and output clock

domains.

It is therefore necessary for the host to configure the OP clock domain to ensure that the

FIFO neither over flows or under flows

Figure 22. Timing block diagram

Table 46. External clock frequency examples, 3.15 Mpixel Raw10 15 fps (CSI-2 or

CCP)

Ext Clk

Freq

Pre-PLL

Clk Div

PLL

multi-

plier

VT Sys

Clk Div

VT pixel

Clk Div

Video

timing

pixel

clock

Line length

Frame

length

MHz

Integer

(Dec)

Integer

MHz

Pixel

Clks

µs

Lines

(Dec)

9.60

63.360

2500

39.46

1690

12.00

106

63.600

2500

39.31

1696

13.00

63.700

2500

39.25

1699

Pre

PLL

sys

Pixel

sys

pixel

Pixel array

Scaler

FIFO

Tx Logic

Output clock domain

Video timing clock domain

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