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VX6854LC 데이터시트(PDF) 73 Page - STMicroelectronics

부품명 VX6854LC
상세설명  QXGA EDOF camera module
PDF  114 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VX6854LC 데이터시트(HTML) 73 Page - STMicroelectronics

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VX6854LC
Electrical characteristics
80
7.3.3
Power supply ripple requirement
It is recommended that the application meets the following requirements on the power
supply signal in 10 kHz to 1.4 MHz.
7.4
System clock - EXTCLK
7.5
Power down control - XSHUTDOWN
Table 53. Ripple requirement
Symbol
Parameter
Max.
Unit
Ripple_VANA
Peak to peak max ripple on analogue power
supply (
10 kHz to 1.4 MHz)
6mV
Ripple_VDIG
Peak to peak max ripple on digital power
supply
50
mV
Table 54. System clock - EXTCLK
Symbol
Parameter
Min.
Max.
Unit
Leakage current
4(1)
1.
With DC coupled square wave clock.
30(2)
2.
With DC VDIG applied.
μA
VCL
DC coupled square wave low level
0
0.3 * VDIG
V
VCH
DC coupled square wave high level
0.7 VDIG
VDIG+0.5V
V
VCAC
AC coupled sine wave
0.5
1.2
V
fEXTCLK
Clock frequency input
6.0 - 1%(3)
3.
Nominal frequencies are 6.0 to 27 MHz with a 1% centre frequency tolerance. Tested at characterization
only.
27 + 1%(3)
MHz
Duty cycles Clock frequency duty cycles
40
60
%
Input jitter
EXTCLK input jitter
-
Refer to Jitter
application
note(4)
4.
STMicroelectronics will provide upon request an application note detailing the EXTCLK input jitter
requirements.
ps
Table 55. Power down control - XSHUTDOWN
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIL
Low level input voltage
0
-
0.3 * VDIG
V
VIH
High level input voltage
0.7 * VDIG
-
VANA
V
IL
Input leakage current(1)
1.
With VGND
≤ VXSHUTDOWN ≤ VDIG
-15
15
μA



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