VX6854LC datasheet(28/114 Pages) STMICROELECTRONICS

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Functional description

VX6854LC

28/114

DocID027110 Rev 2

3.6

Control and video interface formats

Image data is transferred from the VX6854LC using a high speed subLVDS serial link.The

serial control data is transferred to and from the VX6854LC using a CCI bus.

3.6.1

CCP/CSI-2 serial data link

Data signals (DATA+ and DATA-) and clock signals (CLK+ and CLK-) are transferred from

VX6854LC using two pairs of balanced 100

Ω impedance transmission lines.

The transmission line pairs and custom transmitters/receivers realize a very low voltage

differential (subLVDS) signalling scheme that can transfer information in a potentially noisy

environment.

As implemented in VX6854LC, the CCP link supports the transmission of raw bayer data at

3.15 Mpixel resolution up to 20 frame/s at 8-bit or 10-8 bit compressed resolution or

15 frame/s at 10-bit resolution.

As implemented in VX6854LC, the CSI-2 link supports the transmission of raw bayer data at

3.15 Mpixel resolution up to 20 frame/s at 10-bit resolution.

3.6.2

CCI serial control bus

The internal registers in VX6854LC can be configured by a master device using a CCI bus

(SDA, SCL). VX6854LC sends and receives commands over this bus at up to 400 Kbit/s.

The CCI bus uses a device address of 0x20 for writes and 0x21 for reads.

VX6854LC 데이터시트(PDF) 28 Page - STMicroelectronics