AT90LS4433-4AI datasheet(10/126 Pages) ATMEL

10 / 126 page

AT90S/LS4433

1042H–AVR–04/03

General Purpose

Figure 7 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle

access to all registers. The only exceptions are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and

the LDI instruction for load immediate constant data. These instructions apply to the

second half of the registers in the Register File (R16..R31). The general SBC, SUB, CP,

AND, and OR, and all other operations between two registers or on a single register

apply to the entire Register File.

As shown in Figure 7, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y- ,and Z-registers can be set to index any

X-register, Y-register and Z-

The registers R26..R31 have some added functions to their general purpose usage.

These registers are address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y, and Z are defined as:

Figure 8. X-, Y-, and Z-registers

Addr.

$00

$01

$02

…

R13

$0D

General

R14

$0E

Purpose

R15

$0F

Working

R16

$10

Registers

R17

$11

…

R26

$1A

X-register Low Byte

R27

$1B

X-register High Byte

R28

$1C

Y-register Low Byte

R29

$1D

Y-register High Byte

R30

$1E

Z-register Low Byte

R31

$1F

Z-register High Byte

X - register

R27 ($1B)

R26 ($1A)

Y - register

R29 ($1D)

R28 ($1C)

Z - register

R31 ($1F)

R30 ($1E)

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