AT90LS4433-4AI datasheet(54/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is

cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9

bit in the UART Control and Status Register B, UCSRB is set), the TXB8 bit in UCSRB is

transferred to bit nine in the Transmit Shift Register.

On the baud rate clock following the transfer operation to the Shift Register, the start bit

is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has

been shifted out, the Shift Register is loaded if any new data has been written to the

UDR during the transmission. During loading, UDRE is set. If there is no new data in the

UDR Register to send when the stop bit is shifted out, the UDRE Flag will remain set

until UDR is written again. When no new data has been written, and the stop bit has

been present on TXD for one bit length, the TX Complete Flag, TXC, in UCSRA is set.

The TXEN bit in UCSRB enables the UART Transmitter when set (one). When this bit is

cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART

Transmitter will be connected to PD1, which is forced to be an output pin regardless of

the setting of the DDD1 bit in DDRD.

Data Reception

Figure 41 shows a block diagram of the UART Receiver.

Figure 41. UART Receiver

UART CONTROL

AND STAUS

UART CONTROL

AND STAUS

AT90LS4433-4AI 데이터시트(PDF) 54 Page - ATMEL Corporation