AT90LS4433-4AI datasheet(44/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown inTable 16.

Note:

1. The frequency of the Watchdog Oscillator is voltage dependent, as shown in the

Electrical Characteristics section.

The WDR (Watchdog Reset) instruction should always be executed before the

Watchdog Timer is enabled. This ensures that the reset period will be in accordance

with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without

reset, the Watchdog Timer may not start counting from zero.

To avoid unintentional MCU reset, the Watchdog Timer should be disabled or Reset

before changing the Watchdog Timer Prescale Select.

Table 16. Watchdog Timer Prescale Select

(1)

WDP2

WDP1

WDP0

Number of WDT

Oscillator Cycles

Typical Time-out

at VCC = 3.0V

Typical Time-out

at VCC = 5.0V

16K cycles

47 ms

15 ms

32K cycles

94 ms

30 ms

64K cycles

0.19 s

60 ms

128K cycles

0.38 s

0.12 s

256K cycles

0.75 s

0.24 s

512K cycles

1.5 s

0.49 s

1,024K cycles

3.0 s

0.97 s

2,048K cycles

6.0 s

1.9 s

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