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MB9B360R 데이터시트(PDF) 90 Page - Cypress Semiconductor |
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MB9B360R 데이터시트(HTML) 90 Page - Cypress Semiconductor |
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90 / 166 page ![]() Document Number: 002-04872 Rev.*A Page 90 of 166 MB9B360R Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADATA[15:0] VCC ≥ 4.5V 0 10 ns VCC < 4.5V 20 Multiplexed address hold time tCHMADH VCC ≥ 4.5V MCLK×n+0 MCLK×n+10 ns VCC < 4.5V MCLK×n+0 MCLK×n+20 Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16) MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0] |
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