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MB9B360R 데이터시트(PDF) 91 Page - Cypress Semiconductor |
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MB9B360R 데이터시트(HTML) 91 Page - Cypress Semiconductor |
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91 / 166 page ![]() Document Number: 002-04872 Rev.*A Page 91 of 166 MB9B360R Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 4.5V 1 9 ns VCC < 4.5V 12 ns tCHAH VCC ≥ 4.5V 1 9 ns VCC < 4.5V 12 ns MCLK↑→ Multiplexed address delay time tCHMADV MCLK, MADATA[15:0] VCC ≥ 4.5V 1 tOD ns VCC < 4.5V MCLK↑→ Multiplexed data output time tCHMADX VCC ≥ 4.5V 1 tOD ns VCC < 4.5V Note: When the external load capacitance CL = 30pF MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0] |
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