TUSB3410 datasheet(35/92 Pages) TI

35 / 92 page

5–3

5.1.4

USBCTL: USB Control Register (Addr:FFFC)

Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset cannot reset

this register (see Figure 5–1).

765

R/W

R/O

R/W

R/O

R/W

BIT

NAME

RESET

DIR

As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data transfer

direction.

DIR = 0

DIR = 1

USB data-OUT transaction (from host to TUSB3410)

USB data-IN transaction (from TUSB3410 to host)

SIR

SETUP interrupt-status bit. This bit is controlled by the MCU to indicate to the hardware when the SETUP interrupt

is being served.

SIR = 0

SIR = 1

SETUP interrupt is not served. The MCU clears this bit before exiting the SETUP interrupt routine.

SETUP interrupt is in progress. The MCU sets this bit when servicing the SETUP interrupt.

RSV

Reserved = 0

RSV

Reserved = 0

FRSTE

Function reset-connection bit. This bit connects/disconnects the USB function reset to/from the MCU reset.

FRSTE = 0

FRSTE = 1

Function reset is not connected to MCU reset

Function reset is connected to MCU reset

RWUP

Device remote wakeup request. This bit is set by the MCU and is cleared automatically.

RWUP = 0

RWUP = 1

Writing a 0 to this bit has no effect

When MCU writes a 1, a remote-wakeup pulse is generated.

IREN

IR mode enable. This bit is set and cleared by firmware.

IREN = 0

IREN = 1

IR encoder/decoder is disabled, UART mode is selected

IR encoder/decoder is enabled, UART mode is deselected

CONT

Connect/disconnect bit

CONT = 0

CONT = 1

Upstream port is disconnected. Pullup disabled.

Upstream port is connected. Pullup enabled.

TUSB3410 데이터시트(PDF) 35 Page - Texas Instruments

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