 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TMP320C2811PBKA 데이터시트(PDF) 44 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMP320C2811PBKA 데이터시트(HTML) 44 Page - Texas Instruments |
|
|
44 / 147 page  Functional Overview 44 June 2004 SPRS257 3.7 System Control This section describes R281x oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3−7 shows the various clock and reset domains in R281x devices that will be discussed. HSPCLK PLL X1/XCLKIN X2 Power Modes Control Watchdog Block C28x CPU Low-Speed Peripherals SCI-A/B, SPI, McBSP Peripheral Registers High-Speed Peripherals EV-A/B High-Speed Prescaler Low-Speed Prescaler Clock Enables GPIO MUX System Control Registers Peripheral Registers XF_XPLLDIS ADC Registers 12-Bit ADC 16 ADC Inputs HSPCLK LSPCLK I/O I/O Peripheral Reset SYSCLKOUT XRS Reset GPIOs eCAN Peripheral Registers I/O OSC CLKIN NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency. Figure 3−7. Clock and Reset Domains The PLL, clocking, watchdog and low-power modes are controlled by the registers listed in Table 3−11. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
