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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP320C2811PBKA 데이터시트(PDF) 76 Page - Texas Instruments |
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TMP320C2811PBKA 데이터시트(HTML) 76 Page - Texas Instruments |
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76 / 147 page  Peripherals 76 June 2004 SPRS257 Figure 4−11 is a block diagram of the SPI in slave mode. S SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK 4 5 61 2 30 0 1 2 3 SPI Bit Rate State Control SPIRXBUF Buffer Register Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 − 0 SPIBRR.6 − 0 SPICCR.6 SPICTL.3 SPIDAT.15 − 0 SPICTL.1 M S M Master/Slave SPISTS.7 SPIDAT Data Register M S SPICTL.2 SPI Char SPISIMO SPISOMI SPICLK SW2 S M M S SW3 To CPU M SW1 SPITXBUF Buffer Register RX FIFO _0 RX FIFO _1 −−−−− RX FIFO _15 TX FIFO registers TX FIFO _0 TX FIFO _1 −−−−− TX FIFO _15 RX FIFO registers 16 16 16 TX Interrupt Logic RX Interrupt Logic SPIINT/SPIRXINT SPITXINT SPIFFOVF FLAG SPIFFRX.15 16 TX FIFO Interrupt RX FIFO Interrupt SPIRXBUF SPITXBUF SPIFFTX.14 SPIFFENA SPISTE† † SPISTE is driven low by the master for a slave device. Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) |
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