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TMP320C2811PBKA 데이터시트(PDF) 97 Page - Texas Instruments

부품명 TMP320C2811PBKA
상세설명  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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TMP320C2811PBKA 데이터시트(HTML) 97 Page - Texas Instruments

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Electrical Specifications
97
June 2004
SPRS257
6.15 Low-Power Mode Wakeup Timing
Table 6−9 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6−9. IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Pulse duration, external wake-up
Without input qualifier
2*tc(SCO)
Cycles
tw(WAKE-INT)
Pulse duration, external wake-up
signal
With input qualifier
1*tc(SCO) + IQT†
Cycles
t
Delay time, external wake signal to
program execution resume‡
td(WAKE-IDLE)
− Wake-up from SARAM
Without input qualifier
8 * tc(SCO)
Cycles
− Wake-up from SARAM
With input qualifier
8 * tc(SCO) + IQT†
Cycles
† Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
WAKE INT‡
XCLKOUT†
A0−A15
td(WAKE−IDLE)
† XCLKOUT = SYSCLKOUT
‡ WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
tw(WAKE−INT)
Figure 6−10. IDLE Entry and Exit Timing
Table 6−10 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6−10. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(IDLE-XCOH)
Delay time, IDLE instruction
executed to XCLKOUT high
32 * tc(SCO)
12 * tc(CI)
Cycles
t
Pulse duration, external
Without input qualifier
12 * tc(CI)
Cycles
tw(WAKE-INT)
Pulse duration, external
wake-up signal
With input qualifier
(2 + QUALSTDBY)† * tc(CI)
Cycles
td(WAKE-STBY)
Delay time, external wake
signal to program execution
resume‡
td(WAKE-STBY)
− Wake-up from SARAM
Without input qualifier
12 * tc(CI)
Cycles
− Wake-up from SARAM
With input qualifier
12 * tc(CI) + tw(WAKE-INT)
Cycles
† QUALSTDBY is a 6-bit field in the LPMCR0 register.
‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.



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