VT82C596 datasheet(62/96 Pages) ETC

62 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-56-

Function 2 Registers - Universal Serial Bus Controller

7HFKQRORJLHV ,QF

:H &RQQHFW

USB-Specific Configuration Registers

Offset 40 - Miscellaneous Control 1.................................RW

PCI Memory Command Option

Support Memory-Read-Line, Memory-Read-

Multiple, and Memory-Write-and-Invalidate ....

.....................................................default

Only support Memory Read, Memory Write

Commands

Babble Option

Automatically disable babbled port when EOF

babble occurs..........................................default

Don’t disable babbled port

PCI Parity Check Option

Disable PERR# generation.....................default

Enable parity check and PERR# generation

Reserved

........................................ always reads 0

USB Data Length Option

Support TD length up to 1280................default

Support TD length up to 1023

USB Power Management

Disable USB power management...........default

Enable USB power management

1DMA Option

16 DW burst access ................................default

8 DW burst access

0PCI Wait States

Zero wait ................................................default

1One wait

Offset 41 - Miscellaneous Control 2 ................................ RW

USB 1.1 Improvement for EOP

USB Specification 1.1 Compliant.......... default

If a bit stuffing error occurs before EOP, the

receiver will accept the packet

USB Specification 1.0 Compliant

If a bit stuffing error occurs before EOP, the

receiver will ignore the packet

Patch Read / Resume Issue

Enable (Fix the Bug) (Normal Setting).. default

Disable (when one USB port is in reset or

resume status, the controller may not see the

device attached at the other USB port)

Patch 1 Bit-Time EOP

The USB spec says that the device must assert an

EOP in at least two bit times.

Enable (accept 1 bit-time EOP) ............. default

Disable (require 2 bit-time EOP)

Hold PCI Request for Successive Accesses

Disable

Enable .................................................... default

Setting this bit to “enable” causes the system to treat

the USB request as higher priority

Frame Counter Test Mode

Disable................................................... default

1Enable

2Trap Option

Set trap 60/64 status bits only when trap 60/64

enable bits are set................................... default

Set trap 60/64 status bits without checking

enable bits

A20gate Pass Through Option

Pass through A20GATE command sequence

defined in UHCI .................................... default

Don’t pass through Write I/O port 64 (ff)

Reserved

........................................ always reads 0

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