VT82C596 datasheet(67/96 Pages) ETC

67 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-61-

Function 3 Registers - Power Management and SMBus

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 4B-48 – Power Management I/O Base .................RW

31-16 Reserved

........................................ always reads 0

15-7 Power Management I/O Register Base Address.

Port Address for the base of the 128-byte Power

Management I/O Register block, corresponding to

AD[15:7].

The "I/O Space" bit at offset 41 bit-7

enables access to this register block. The definitions

of the registers in the Power Management I/O

following

the

Power-Management-Specific

PCI

Configuration register descriptions and the Power

Management Subsystem overview.

6-0

0000001b

Offset 4C – Host Bus Power Management Control........RW

7-4

Thermal Duty Cycle (THM_DTY)

This 4-bit field determines the duty cycle of the

STPCLK# signal when the THRM# pin is asserted

low. The field is decoded as follows:

0000 Reserved

0001 0-6.25%

0010 6.25-12.50%

0011 18.75-25.00%

0100 31.25-37.50%

0101 37.50-43.75%

0110 43.75-50.00%

0111 50.00-56.25%

1000 56.25-62.50%

1001 62.50-68.75%

1010 68.75-75.00%

1011 75.00-87.50%

1100 75.00-81.25%

1101 81.25-87.50%

1110 87.50-93.75%

1111 93.75-100%

3-2

Reserved

........................................ always reads 0

SRAM ZZ

Disable ...................................................default

Enable (power down the cache SRAM)

CPU Stop Grant Cycle Select

From Halt and Stop Grant Cycle ............default

From Stop Grant Cycle

This bit is combined with I/O space Rx2C[3] for

controlling the start of STPCLK# assertion during

system suspend mode:

Rx2C[3]

Rx4C[0]

Function 3

I/O Space

Cfg Space

STPCLK# Assertion

Immediate

Wait for CPU Halt

/ Stop Grant cycle

Wait for CPU

Stop Grant cycle

Offset 4D – Clock Stop Control ....................................... RW

7-3

Reserved

........................................ always reads 0

Internal Clock Stop for PCI Idle

Disable................................................... default

1Enable

Internal Clock Stop During C3

Disable................................................... default

1Enable

Internal Clock Stop During Suspend

Disable................................................... default

1Enable

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