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STA310 데이터시트(PDF) 44 Page - STMicroelectronics

부품명 STA310
상세설명  62-CH. MULTISTANDARD AUDIO DECODER
PDF  90 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA310 데이터시트(HTML) 44 Page - STMicroelectronics

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STA310
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384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_FRACL_176
Frac Low Coefficient
Address: 0xBB
Type: R/W
Software Reset: 0x3
Hardware Reset: UND
Description:
This register must contain a FRACL value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_FRACH_176
Frac High Coefficient
Address: 0xBC
Type: R/W
Software Reset: 0x9
Hardware Reset: UND
Description:
This register must contain a FRACH value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_XDIV_176
X Divider Coefficient
Address: 0xBD
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a XDIV value that enables
the
audio
PLL
to
generate
a
frequency
of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_MDIV_176
M Divider Coefficient
Address: 0xBE
Type: R/W
Software Reset: 0x09
Hardware Reset: UND
Description:
This register must contain a MDIV value that enables
the
audio
PLL
to
generate
a
frequency
of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_NDIV_176
N Divider Coefficient
76
54
321
0
FRACL
76
54
321
0
FRACH
76
54
321
0
XDIV
76
54
321
0
MDIV
76
54
321
0
NDIV



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