STA310 datasheet(49/90 Pages) STMICROELECTRONICS

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STA310

Hardware: Reset:UND

Description:

The table below shows the relationship between the value of the IEC divider and the value of the PCM divider.

SPDIF_STATUS

SPDIF status bit

Address: 0x61

Type: R/W

Software Reset: NC

Hardware: Reset UND

Description:

Bitfield

Description

DIV[4:0]

This field is the DAC_PCMCLK divider. It must be set according to the formula:

in 16 bit mode: IECDIV=(1+PCMDIV)/2-1; in 32 bit mode: IECDIV=PCMDIV

RND

This bit is used to have a "16-bit rounding" on the SPDIF (when in PCM mode):

0: no rounding,

1: rounding.

This bit has no effect on the precision of analogue data

SYNC MUTE Mode, must be set to zero.

LAT

Configures the latency mode between the SPDIF output (in mode compressed) and the Audio output.

0: Auto-Latency: The latency is the transmission time for 2/3 of the payload, plus the time to decode

an audio block.

For MPEG Auto-Latency, the latency is the following time depending of the sampling frequency in the

incoming bitstream: MPEG 48KHz: 20.90ms, MPEG 44.1KHz: 22.95ms, MPEG 32KHz: 32.53ms.

1: User-programmable latency - the

SPDIF_LATENCY register is used.

PCM Divider Value

Mode Description

IEC Divider Value

DAC_PCMCLK = 384Fs, DAC is 16-bit mode

DAC_PCMLK = 256 Fs, DAC is 16-bit mode

DAC_PCMLK = 384 Fs, DAC is 32-bit mode

DAC_PCMLK = 256 Fs, DAC is 32-bit mode

543210

SFR

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