PCF8833USLASH2DA datasheet(50/112 Pages) PHILIPS

50 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

6.2.34

SUPER FRAME INVERSION

The Super frame inversion command (FINV), which is the inversion of the row functions after all rows are written to can

be switched off for the PCF8833. When switched off, the inversion of the row functions will then only be done with N-line

inversion. Inversion of the row functions is needed so as to avoid a DC component over the LCD display. A detailed

description of the N-line inversion is given in Section 6.2.45.

The FINV control bit reset state is defined in Table 52.

Table 52 Super frame inversion register bits

Table 53 Super frame inversion reset state

6.2.35

DATA ORDER

The data order (DOR) of the data which will be written into the RAM can be changed (swapped).

The DOR command is explained and the reset state defined in Table 55.

Table 54 Data order register bits

Table 55 Data order reset state

6.2.36

TEMPERATURE COMPENSATED FRAME FREQUENCY

The PCF8833 incorporates a temperature segmented frame frequency programming; see Section 6.2.41. This

segmented frame frequency can be disabled by using the temperature compensated frame frequency (TCDFE)

command.

The TCDFE control bit reset state is defined in Table 57.

When the non-segmented frame frequency is chosen, the frame frequency in segment B (DFB) is valid;

see Section 6.2.41.

Table 56 Temperature compensated frame frequency register bits

D/C

6543210

DEFAULT

FINV

B9H

BIT

LOGIC 0

LOGIC 1 (RESET STATE)

FINV

super frame inversion is off

super frame inversion is on

D/C

6543210

DEFAULT

DOR

BAH

BIT

LOGIC 0 (RESET STATE)

LOGIC 1

DOR

normal data order

MSB/LSB transposed for RAM data

D/C

6543210

DEFAULT

TCDFE

BDH

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