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PCF8833U/2DA 데이터시트(PDF) 89 Page - NXP Semiconductors

부품명 PCF8833U/2DA
상세설명  STN RGB - 132 X 132 X 3 driver
PDF  112 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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2003 Feb 14
89
Philips Semiconductors
Objective specification
STN RGB - 132
× 132 × 3 driver
PCF8833
15.7
Example of filling the shift register
Table 96 shows the sequence of commands to fill the OTP matrix as defined in Table 93.
Table 96 Sequence for filling the OTP matrix
Notes
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be logic 0.
2. The chip stays in shift operation as long as D/C is logic 1.
15.8
Programming flow
In order to program an OTP cell, the associated register must be set to logic 1 and a programming voltage of 8 V should
to be applied to pins VOTP(gate) and VOTP(drain) for 50 ms. It is strongly recommended to use the sequence shown in
Table 97 to program the OTP cells. In any event the requirements stated in Section 15.9 must be met.
Important: Whenever a new row in the OTP matrix is selected (change of ORA[2:0]), the OTP cells must not be
connected to pin VOTP(drain) (set OPE = 0). For an example see steps 9 to 11 in Table 97.
STEP
D/C
COMMAND BYTE(1)
ADDR
DESCRIPTION
76543210
1
000000001
01H
reset (may also be hardware
reset)
2
wait 1 ms for refresh to take
effect
3
011110000
F0H
enter CALMM mode
1
X
X
0
0
0
X
0
1
01H
ORA = 000; OPE = 0;
CALMM = 1
4
011110001
F1H
send OTPSHTIN; note 2
shift15
1
X
X
000000
00H
set PVB[3:0]; BRS and TRS
shift14
1
X
X
000000
00H
set FVB[3:0]; 0 and EFD
shift13
1
X
X
000000
00H
set PVPR[8:3]
shift12
1
X
X
000000
00H
set PVPR[2:0] and FVPR[8:6]
shift11
1
X
X
000000
00H
set FVPR[5:0]
shift10
1
X
X
000000
00H
set SLD[2:0] and SLC[2:0]
shift9
1
X
X
000000
00H
set SLB[2:0] and SLA[2:0]
shift8
1
X
X
000000
00H
set PS[1:0]; FS[1:0] and ID3[7:6]
shift7
1
X
0000000
00H
set ID3[5:0] and ID2[7]
shift6
1
X
0000000
00H
set ID2[6:0]
shift5
1
X
0000000
00H
set DF8[6:0]
shift4
1
X
0000000
00H
set DFD[6:0]
shift3
1
X
0000000
00H
set DFC[6:0]
shift2
1
X
0000111
07H
set DFB[6:0]
shift1
1
X
0010001
11H
set DFA[6:0]
shift0
1
X
0011010
1AH
set MMVOP[5:0] and SEAL
5
011110000
F0H
exit CALMM mode; if required
1
X
X
0
0
0
X
0
0
00H
ORA = 000; OPE = 0;
CALMM = 0



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