PCF8833USLASH2DA datasheet(78/112 Pages) PHILIPS

78 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

Notes

1. VDD2 and VDD3 always have to be larger than or equal to VDD1.

2. Not directly observable at any pin.

3. After calibration the following fosc can be expected at 25 °C: 600 kHz ±4%; at different temperatures an additional

variation of +0.12%/

°C will not be exceeded.

4. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

VIL and VIH with an input voltage swing of VSS1 to VDD1.

5. The initialization incorporates the start-up of the internal circuitry including the readout of the OTP cells. The start-up

time for the internal voltage generation is not included.

6. The input signal rise time and fall time (tr and tf) are specified at 15 ns or less. When the cycle time is used at high

speed, the specification is tr +tf ≤ (tCYC − tCCLW − tCCHW) or tr +tf ≤ (tCYC – tCCLR − tCCHR).

7. CS can be permanently tied LOW.

8. The output disable time and read access time is applicable after the second read cycle (see Fig.40).

9. For VDD1 = 1.8 V possible variation of tOH is between 40 and 80 ns for a temperature range of −40 to +85 °C.

handbook, full pagewidth

MGU966

VDD1

VIL

VIH

VIL

VIH

VDD1

RES

Status

resetting

normal operation

Status

resetting

normal operation

Interface:

commands/data

not accepted

accepted

not accepted

accepted

tRI

tRSS

tSU;RESL

tW(RESL)

tRT

tW(RESL)

tRT

Fig.50 Reset timing.

PCF8833U/2DA 데이터시트(PDF) 78 Page - NXP Semiconductors

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