MCP3918A1T-ESLASHML datasheet(44/88 Pages) MICROCHIP

44 / 88 page

MCP3918

DS20005287A-page 44

 2014 Microchip Technology Inc.

6.2

Control Byte

The Control byte of the MCP3918 contains two device

Address bits (A<6:5>), five register Address bits

(A<4:0>) and a Read/Write bit (R/W). The first byte

transmitted to the MCP3918 in any communication is

always the Control byte. During the Control byte

transfer, the SDO pin is always in a high-impedance

state. The MCP3918 interface is device addressable

(through A<6:5>), so that multiple chips can be present

on the same SPI bus with no data bus contention, even

if they use the same CS pin and a provided half-duplex

SPI interface, with a different address identifier. This

functionality enables, for example, a Serial EEPROM

like 24AAXXX/24LCXXX or 24FCXXX. Moreover, it

enables the MCP3918 to share all the SPI pins and to

consume less I/O pins in the application processor,

since all these Serial EEPROM circuits use

A<6:5> = 00.

FIGURE 6-1:

Control Byte.

The default device address bits are A<6:5> = 01

(contact the Microchip factory for other available device

address bits). For more information, see the Product

Identification System

section. The register map is

defined in Table 9-1.

6.3

Reading from the Device

The first register read on the SDO pin is the one defined

by the address (A<4:0>) given in the Control byte. After

this first register is fully transmitted, if the CS pin is

maintained logic low, the communication continues

without an additional Control byte and the SDO pin

transmits

another

with

the

address

automatically incremented.

Four different read mode configurations can be defined

through the READ<1:0> bits in the STATUSCOM

“Continuous

Communications,

Looping

and Table 9-2). The data on SDO is

clocked out of the MCP3918 on the falling edge of

SCK. The reading format for each register is defined in

Section 5.5 “ADC Output Coding”

FIGURE 6-2:

Read on a Single Register with 24-bit Format (WIDTH_DATA<1:0> = 01,

SPI Mode 1,1).

A<6> A<5> A<4> A<3> A<2> A<1> A<0> R/W

Device

Address

Read/

Write

READ Communication (SPI mode 1,1)

Don’t care

SCK

SDI

SDO

DATA<0>

Hi-Z

Device latches SDI on rising edge

Device latches SDO on falling edge

R/W

High Z

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