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MCP3918A1T-E/ML 데이터시트(PDF) 72 Page - Microchip Technology

부품명 MCP3918A1T-E/ML
상세설명  3V Single-Channel Analog Front End
PDF  88 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3918A1T-E/ML 데이터시트(HTML) 72 Page - Microchip Technology

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MCP3918
DS20005287A-page 72
 2014 Microchip Technology Inc.
bit 14
EN_INT:
Enable the CRCREG interrupt function
1
=
The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin
(DR) will become logic low and stays logic low if a CRCREG checksum error happens. This
interrupt is cleared if the LOCK<7:0> value is made equal to the PASSWORD value (0xA5).
0
=
The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG<15:0>
bits are still calculated properly and can still be read in this mode.
bit 13-12
Reserved:
These bits should be kept equal to '0' at all times.
bit 11
EN_MDAT:
Enable Modulator Output
1
=
MDAT0 output is enabled
0
=
MDAT0 output is disabled (DEFAULT)
bit 10-1
Unimplemented:
Read as ‘0’
bit 0
DRSTATUS:
Data Ready status bit
DRSTATUS
= 1 - Channel CH0 data is not ready (DEFAULT)
DRSTATUS
= 0 - Channel CH0 data is ready. The status bit is set back to '1' after reading the
STATUSCOM register. The status bit is not set back to '1' by the read of the
corresponding channel ADC data.
REGISTER 9-5:
STATUSCOM REGISTER (CONTINUED)



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