GC2011A datasheet(39/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

6.7

SNAPSHOT MODE CONTROL REGISTERS

The snapshot memory is divided into two halves, 128 words by 16 bits each. SNAP_REGA controls the A-half

of the snapshot memory, SNAP_REGB controls the B-half.

ADDRESS 8:

SNAP_REGA

ADDRESS 9:

SNAP_REGB

BIT

TYPE

NAME

DESCRIPTION

0,1 (LSBs)

R/W

SEL_IN

Selects the snapshot source as:

SEL_IN

DESCRIPTION

IB[0:11]

IA[0:11]

OA[0:15]

OB[0:15]

2,3

R/W

SNAP_RATE

Determines the rate at which samples are stored according to:

SNAP_RATE

DESCRIPTION

every clock, full rate samples

every other clock, half rate samples

invalid

3every 4th clock, quarter rate samples.

4-7

R/W

SNAP_DELAY

Delay from snapshot trigger in blocks of 128 samples until start of

snapshot. The delay is:

128*SNAP_DELAY*(SNAP_RATE+1)

clock cycles where SNAP_DELAY ranges from 0 to 15. This control

allows the user to start the A or B-half snapshot a fixed number of

samples after the other half’s snapshot.

R/W

SNAP_HOLD

Do not start a new snapshot. This control lets the user start one

half of the snapshot memory and not the other.

R/W

BYTE_MODE

This control reorganizes the memory half into 256 bytes instead

of 128 words. The upper 8 bits of the input source are stored.

10-15(MSB)

R/W

unused

In the BYTE_MODE the memory is reorganized so that the first 128 bytes of the 256 byte snapshot are stored

in the least significant bytes of the 128 word memory and the second 128 bytes are stored in the most significant bytes

of the 128 word memory.

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