Texas Instruments Incorporated

- 14 -

GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

3.1

FULL RATE

The full rate filter implements Equation (1) using the structures shown in Figure 2. The control register settings

which configure the chip in the full rate modes are tabulated below:

The coefficients can be stored in coefficient register 1 or 3 of each filter cell. Coefficient registers 0 and 2 are

not used in the full rate mode. To store coefficients h(k) in register 1 of each filter cell use the memory addresses

BASE+4*k+1, where BASE is 128 for A-path or cascaded filters and is 192 for B-path filters, and

k ranges from 0 to N-1 for filters without symmetry,

k ranges from 0 to N/2-1 for filters with even symmetry, or

k ranges from 0 to (N-1)/2 for filters with odd symmetry.

To store the coefficients in register 3 of each filter cell use the addresses BASE+4*k+3.

The control register settings in Table 2 assume the coefficients are stored in coefficient register 1 of each filter

each filter cell is synchronized to the clock (CK) so that the user can switch between taps stored in register 1 and register

3 without causing any undesirable transients in the filter’s operation. This is useful for adaptive filter applications.

Table 2: Full Rate Mode Control Register Settings

Symmetry

Dual Path or

Cascaded

# of Taps

(N)

A-PATH

B-PATH

Cascade

Latency

REG0

REG1

REG0

REG1

REG

None

Dual

16

20D8

6000

00D8

6000

2000

44

Cascaded

32

20D8602800D86000

9E00

60

Even

Dual

32

20D8

6108

00D8

6108

2000

44

Cascaded

64

20D8612800D86108

9E00

60

Odd

Dual

31

20D8

6181

00D8

6181

2000

44

Cascaded

63

20D8

61A8

00D8

6181

9E00

60