GC2011A datasheet(44/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

7.5

AC CHARACTERISTICS

Table 20: AC Characteristics (-40 TO +85oC Ambient, unless noted)

PARAMETER

SYMBOL

3.1V to 3.5V

UNITS

NOTES

MIN

MAX

Clock Frequency

FCK

0.01

106

MHz

2, 3

Clock low period (Below VIL)tCKL

3.8

Clock high period (Above VIH)tCKH

3.6

Data setup before CK goes high

(AI, BI, SI, SN or CKEN)

tSU

3.0

Data hold time after CK goes high

tHD

1.0

Data output delay from rising edge of CK.

(AO, BO, DAV, or SO)

tDLY

1.0

8.0

2,4

Data to tristate delay

(AO, BO, AOF or BOF to hiZ from AOE or BOE)

tDZ

2.0

5.0

Tristate to data output delay

(AO, BO, AOF, or BOF valid from AOE or BOE)

tZD

3.0

Note 1

8.0

Note 2

Control Setup before CE and RE, or WE go low (A, WE during

read, and A, RE, C during write) See Figure 3.

tCSU

5.0

Control hold after CE,RE, or WE go high (A, WE during read,

and A, RE, C during write) See Figure 3.

tCHD

5.0

Control enable CE or WE pulse width

(Write operation) See Figure 3.

tCSPW

30.0

2,5

Control output delay CE and RE low to C

(Read Operation) See Figure 3.

tCDLY

35.0

2,6

Control tristate delay after CE or RE go high. See Figure 3.

tCZ

10.0

Quiescent supply current

(VIN=0 or VCC, FCK = 0, or POWER_DOWN=1)

ICCQ

2.0

Supply current

(FCK = 80 MHz)

ICC

500.0

2, 7

Notes:

1. Controlled by design and process and not directly tested. Verified on initial part evaluation.

2. Each part is tested at 85 deg C for the given specification.

3. The chip may not operate properly at clock frequencies below MIN and MAX.

4. Capacitive output load is 20pf. Delays are measured from the rising edge of the clock to the output level rising

above or falling below 1.3v.

5. tCSPW must be at least five clock cycles wide if the SYNC_COEF control bit is set (See Section 6.3).

6. Capacitive output load is 80pf.

7. Current changes linearly with voltage and clock speed.

Icc (MAX)

VCC

3.3

------------



 FCK

80M

-----------





500mA

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