STLUX385ATR datasheet(37/126 Pages) STMICROELECTRONICS

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STLUX

I/O multifunction signal configuration

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7.2.3

Port P0 I/O functional multiplexing signal

Figure 10 shows an outline view of the Port P0 multifunction multiplexing scheme.

Figure 10. Port P0 I/O functional multiplexing scheme

Note:

Where the “A/F(s) in” and “A/F(s) out” signals are defined in Section 6.2 on page 32.

Verify pin availability in Table 4: Pin description on page 32.

On the STLUX325A device:



P0_ODR [1:0] bits must be keep clear.



P0 [6] is a multifunction signal configurable through the MSC_IOMXP2 [7] and

AFR_IOMXP2 [7] register bits - for further details refer to Section 7.4.



Port P0 [6] signal is controlled by P0_ODR [6] and P0_IDR [6] GPIO0 registers.

On the STLUX285A device:



P0_ODR [1:0] bits must be keep clear.

7.2.4

P0 interrupt capability

Port P0 signals may be configured to generate maskable (IRQ) and un-maskable (NMI)

interrupts by programming the MSC_CFGP0<n> and the MSC_STSP0 registers (n = index

port signal). This functionality is not applicable to the bit port P0 [6] on the STLUX325A and

on the port P0:[1:0] on STLUX285A.

The interrupt request may be configured to wake-up the IC device from the WFI (wait for

interrupt), AHalt (active Halt) and Halt power saving state.

7.2.5

P0 programmable pull-up and speed feature

The I/O speed and pad pull-up resistance (47 k

) of the port P0 may be configured through

the GPIO0 internal registers.

The pull-up resistance of the multifunction signal P0 [6] is always enabled on the

STLUX325A.

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