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UCS1002-1 데이터시트(PDF) 73 Page - Microchip Technology

부품명 UCS1002-1
상세설명  Programmable USB Port Power Controller with Charger Emulation
PDF  116 Pages
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제조업체  MICROCHIP [Microchip Technology]
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UCS1002-1 데이터시트(HTML) 73 Page - Microchip Technology

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Programmable USB Port Power Controller with Charger Emulation
Datasheet
SMSC UCS1002
73
Revision 1.4 (07-16-13)
DATASHEET
10.3
Status Registers
The Status registers store bits that indicate error conditions as well as Attach Detection and Removal
Detection. Unless otherwise noted, these bits will operate as described when the UCS1002 is
operating in Stand-alone mode.
10.3.1
Other Status - 0Fh
Bit 5 - ALERT_PIN - Reflects the status of the ALERT# pin. When set, indicates that the ALERT# pin
is asserted low. This bit is set and cleared as the ALERT# pin changes states.
Bit 4 - ADET_PIN - Reflects the status of the A_DET# pin. When set, indicates that the A_DET# pin
is asserted low. This bit is set and cleared as the A_DET# pin changes states.
APPLICATION NOTE: If S0 is '1', PWR_EN is enabled, and VS is not present, the ADET_PIN bit will cycle if the
current draw exceeds the current capacity of the bypass switch.
Bit 3 - CHG_ACT - This bit is automatically set when IBUS > IBUS_CHG and cleared when IBUS <
IBUS_CHG.
APPLICATION NOTE: The CHG_ACT bit does not indicate that a portable device has accepted one of the charger
emulation profiles. This bit will cycle during the Dedicated Charger Emulation Cycle.
Bit 2 - EM_ACT - Indicates that the UCS1002 is in the Active state and emulating. The actual profile
that is being applied is identified by PRE_EM_SEL[3:0] (see Section 10.12.1, "Applied Charger
Emulation - 30h"). This bit is set and cleared automatically.
APPLICATION NOTE: The EM_ACT bit does not indicate that a portable device has accepted one of the emulation
profiles. This bit will cycle during the Dedicated Charger Emulation Cycle.
Bits 1 - 0 - EM_STEP[1:0] - Indicates which stimulus / response pair is currently being applied by the
charger emulation profile as shown in Table 10.5. These bits are set and cleared automatically. Note
Table 10.4 Status Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0Fh
R
Other
Status
-
-
ALERT
_PIN
ADET_
PIN
CHG
_ACT
EM
_ACT
EM_STEP[1:0]
00h
10h
See
Text
Interrupt
Status
ERR
DISCH
ARGE_
ERR
RESET
MIN_
KEEP_
OUT
TSD
OVER
_VOLT
BACK_
VOLT
OVER
_LIM
00h
11h
R / R-C
General
Status
RATION
-
-
CC_
MODE
TREG
LOW_
CUR
REM
ATT
00h
12h
R
Profile
Status 1
NO_ HS
-
-
VS_LO
W
CUST
DCP
CDP
PT
00h
13h
R
Profile
Status 2
-
LG7
LG6
LG5
LG4
LG3
LG2
LG1
00h
14h
R
Pin Status
-
PWR_
EN_PI
N
M2_
PIN
M1_
PIN
EM_
EN_
PIN
SEL_P
IN
PWR_STATE
[1:0]
00h



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