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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN8741Ai-EN 데이터시트(PDF) 89 Page - Microchip Technology |
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LAN8741Ai-EN 데이터시트(HTML) 89 Page - Microchip Technology |
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89 / 106 page  2013-2015 Microchip Technology Inc. DS00001988A-page 89 LAN8741A/LAN8741Ai 5.6.3 MII INTERFACE TIMING This section specifies the MII interface transmit and receive timing. Please refer to Section 3.4.1, "MII" for additional details. Note 1: 40 ns for 100BASE-TX operation, 400 ns for 10BASE-T operation. 2: Timing was designed for system load between 10 pF and 25 pF. FIGURE 5-3: MII RECEIVE TIMING TABLE 5-9: MII RECEIVE TIMING VALUES Symbol Description Min. Typ. Max. Unit Note tclkp RXCLK period (see Note 1)ns tclkh RXCLK high time tclkp * 0.4 tclkp * 0.6 ns tclkl RXCLK low time tclkp * 0.4 tclkp * 0.6 ns tval RXD[3:0], RXDV, RXER output valid from rising edge of RXCLK 28.0 ns (see Note 2) tinvld RXD[3:0], RXDV, RXER output invalid from rising edge of RXCLK 10.0 ns (see Note 2) RXCLK (OUTPUT) tclkh tclkl tclkp tval tinvld tval tval tinvld RXDV, RXER (OUTPUTS) RXD[3:0] (OUTPUTS) |
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