LAN91C111 datasheet(89/125 Pages) MICROCHIP

89 / 125 page

LAN91C111

DS00002276A-page 90

 2011-2016 Microchip Technology Inc.

12.0

APPLICATION CONSIDERATIONS

The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level

implications and sample configurations for the most relevant bus types. All applications are based on buffered architec-

tures with a private SRAM bus.

12.1

Fast Ethernet Slave Adapter

Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.

Adapter requires:

LAN91C111 chip

Serial EEPROM (93C46)

Some bus specific glue logic

Target systems:

VL Local Bus 32 bit systems

High-end ISA or non-burst EISA machines

EISA 32 bit slave

12.2

VL Local Bus 32 Bit Systems

On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit peripheral in terms of the

bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to

the DATA REGISTER could use byte, word, or dword instructions.

TABLE 12-1:

VL LOCAL BUS SIGNAL CONNECTIONS

VL Bus Signal

LAN91C111 Signal

Notes

A2-A15

Address bus used for I/O space and register decoding, latched by nADS

rising edge, and transparent on nADS low time.

M/nIO

AEN

Qualifies valid I/O decoding - enabled access when low. This signal is

latched by nADS rising edge and transparent on nADS low time.

W/nR

Direction of access. Sampled by the LAN91C111 on first rising clock that

has nCYCLE active. High on writes, low on reads.

nRDYRTN

Ready return. Direct connection to VL bus.

nLRDY

nSRDY and some

logic

nSRDY has the appropriate functionality and timing to create the VL

nLRDY except that nLRDY behaves like an open drain output most of

the time.

LCLK

Local Bus Clock. Rising edges used for synchronous bus interface

transactions.

nRESET

RESET

Connected via inverter to the LAN91C111.

nBE0 nBE1

nBE2 nBE3

nBE0 nBE1 nBE2

nBE3

Byte enables. Latched transparently by nADS rising edge.

nADS

nADS, nCYCLE

Address Strobe is connected directly to the VL bus. nCYCLE is created

typically by using nADS delayed by one LCLK.

IRQn

INTR0

Typically uses the interrupt lines on the ISA edge connector of VL bus

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