LAN91C111 datasheet(93/125 Pages) MICROCHIP

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LAN91C111

DS00002276A-page 94

 2011-2016 Microchip Technology Inc.

12.4

EISA 32 Bit Slave

On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an

I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is

externally derived from nCMD edges. Given that the access will be at least 1.5 to 2 clocks (more than 180ns at least)

there is no need to negate EXRDY, simplifying the EISA interface implementation. As a DMA Slave, the LAN91C111

accepts burst transfers and is able to sustain the peak rate of one doubleword every BCLK. Doubleword alignment is

assumed for DMA transfers. The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits

wait states.

FIGURE 12-2:

LAN91C111 ON ISA BUS

TABLE 12-3:

EISA 32 BIT SLAVE SIGNAL CONNECTIONS

EISA Bus Signal

LAN91C111 Signal

Notes

LA2-LA15

A2-A15

Address bus used for I/O space and register decoding, latched by

nADS (nSTART) trailing edge.

M/nIO

AEN

Qualifies valid I/O decoding - enabled access when low. These

signals are externally ORed. Internally the AEN pin is latched by

nADS rising edge and transparent while nADS is low.

Latched W-R

combined with

nCMD

nRD

I/O Read strobe - asynchronous read accesses. Address is valid

before its leading edge. Must not be active during DMA bursts if

DMA is supported.

A1-A15, AEN

RESET

nBE2, nBE3

D0-D15

INTR0

nRD

nWR

nBE0

nBE1

nLDEV

LAN91C111

A1-A15, AEN

RESET

VCC

D0-D15

IRQ

nIORD

nIOWR

nSBHE

nIOCS16

O.C.

ISA BUS

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