LAN9211 datasheet(111/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

111

Revision 2.9 (03-01-12)

DATASHEET

5.4.6

MII_ACC—MII Access Register

This register is used to control the Management cycles to the PHY.

5.4.7

MII_DATA—MII Data Register

This register contains either the data to be written to the PHY register specified in the MII Access

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

BITS

DESCRIPTION

31-16

Reserved

15-11

PHY Address: For every access to this register, this field must be set to 00001b.

10-6

MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.

5-2

Reserved

MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data

MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.

This bit must read a logical 0 before writing to this register and MII data register.

The LAN driver software must set (1) this bit in order for the LAN9211 to read or write any of the MII

PHY registers.

During a MII register access, this bit will be set, signifying a read or write access is in progress. The

MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The

MII data register is invalid until the MAC has cleared this bit during a PHY read operation.

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

BITS

DESCRIPTION

31-16

Reserved

15-0

MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to

be written to the PHY before an MII write operation.

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