LAN9211 datasheet(129/147 Pages) SMSC

129 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

129

Revision 2.9 (03-01-12)

DATASHEET

6.2

PIO Reads

PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters

in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing

diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both

of these control signals must go high between cycles for the period specified.

Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read

cycles.

Note: The “Data Bus” width is 16 bits

Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either

or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.

Figure 6.1 PIO Read Cycle Timing

Table 6.3 PIO Read Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Read Cycle Time

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address Setup to nCS, nRD Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Data Bus

nCS, nRD

A[7:1]

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