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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9211 데이터시트(PDF) 130 Page - SMSC Corporation |
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LAN9211 데이터시트(HTML) 130 Page - SMSC Corporation |
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130 / 147 page  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support Datasheet Revision 2.9 (03-01-12) 130 SMSC LAN9211 DATASHEET 6.3 PIO Burst Reads In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between bursts for the period specified. Note: The “Data Bus” width is 16 bits Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Figure 6.2 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing SYMBOL DESCRIPTION MIN TYP MAX UNITS tcsh nCS, nRD Deassertion Time 13 ns tcsdv nCS, nRD Valid to Data Valid 30 ns tacyc Address Cycle Time 45 tasu Address Setup to nCS, nRD valid 0 ns tadv Address Stable to Data Valid 40 tah Address Hold Time 0 ns tdon Data Buffer Turn On Time 0 ns tdoff Data Buffer Turn Off Time 7 ns tdoh Data Output Hold Time 0 ns Data Bus nCS, nRD A[7:5] A[4:1] |
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