| 전자부품 데이터시트 검색엔진 |
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TDP158 데이터시트(PDF) 49 Page - Texas Instruments |
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TDP158 데이터시트(HTML) 49 Page - Texas Instruments |
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49 / 55 page ![]() xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx 1 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 65 NŸ 65 NŸ VCC GND GND VCC VCC 2k/65 NŸ VCC VCC VCC 5V 5V 65 NŸ 65 NŸ 2 NŸ 2 NŸ 2 NŸ 2 NŸ GND Place VCC and VDD decoupling caps as close to VCC and VDD pins as possible Match High Speed traces length as close as possible to minimize Ske Match High Speed traces length as close as possible to minimize Ske HPD_SRC HPD_SNK IN_D2p/n IN_D1p/n IN_D0p/n OUT_D2p/n IN_CLKp/n I2C_EN A1/EQ2 OUT_D1p/n OUT_D0p/n OUT_CLKp/n SDA_SNK SCL_SNK SDA_SRC SDA_CTL SCL_SRC SCL_CTL VSADJ A0/EQ1 DE SLEW GND TERM SWAP 65 NŸ 2k/65 NŸ For I2C only Pop pull up and use 2 NŸ For DE and SWAP only Pop pull up or pull down and use 65 NŸ 49 TDP158 www.ti.com SLLSEX2 – DECEMBER 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 11.2 Layout Example The differential input lanes and differential output lanes should be separated as close to the TDP158 as feasible in order to minimize crosstalk. Adding a ground flood plain between each differential lane further reduces crosstalk and thus improves signal integrity at high speed data rates. Figure 51. Example Layout for Source Side Application |
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