5

TDP158

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SLLSEX2 – DECEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential voltages, are with respect to network ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

MAX

UNIT

VCC

–0.3

4

V

VDD

–0.3

1.4

V

Voltage Range

Main Link Input Differential Voltage (IN_Dx)

–0.3

1.56

V

Main Link Input Single Ended on Pin

–0.3

1.4

V

TMDS Output ( OUT_Dx)

–0.3

4

V

HPD_SRC, VSADJ, SDA_CTL/PRE, OE,

A1/EQ2, A0/EQ1, TERM, I2C_EN, SLEW,

SCL_CTL/SWAP, SDA_SRC, SCL_SRC

–0.3

4

V

HDP_SNK, SDA_SNK, SCL_SNK

–0.3

6

V

Continuous power dissipation

See Thermal Information

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

Charged-device model (CDM), per JEDEC specification JESD22-

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Supply Voltage Nominal Value 3.3 V

3

3.6

V

Supply Voltage Nominal Value 1.1 V

1

1.27

V

Junction temperature

–40

105

°C

Operating free-air temperature (TDP158)

0

85

°C

Operating free-air temperature (TDP158I)

–40

85

°C

MAIN LINK DIFFERENTIAL PINS

Peak-to-peak input differential voltage See Figure 19

75

1200

mV

The input differential voltage Peak-to peak DC level, See Figure 19

200

1200

mV

Input Common Mode Voltage (Internally Biased)

0.5

0.9

V

Data rate

0.25

6

Gbps

VSADJ

TMDS compliant swing voltage bias resistor Nominal 6 k

Ω

–1%

1%

DDC, I2C, HPD, AND CONTROL PINS

DC Input Voltage

HDP_SNK, SDA_SNK, SCL_SNK,

–0.3

5.5

V

SDA_SRC, SCL_SRC; All other Local I2C, and

control pins

–0.3

3.6

V

Low-level input voltage at DDC

V

Low-level input voltage at HPD

0.8

V

Low-level input voltage at SDA_CTL/PRE, OE, A1/EQ2, A0/EQ1, TERM,

I2C_EN, SLEW, SCL_CTL/SWAP pins only

0.3

V

Mid-Level input voltage at A1/EQ2, A0/EQ1, TERM, SLEW pins only

1.2

1.6

V