AM79C970 datasheet(22/168 Pages) AMD

22 / 168 page

P R E L I M I N A R Y

AMD

1-889

Am79C970

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

PCnet-PCI controller uses non-burst as well as burst cy-

cles for read and write access to the main memory.

Basic Non-Burst Read Cycles

The PCnet-PCI controller uses non-burst read cycles to

access the initialization block and the receive and trans-

mit descriptor entries. Some of the read accesses to the

transmit buffer memory are also in non-burst mode. All

PCnet-PCI controller non-burst read accesses are of

the PCI command type Memory Read (type 6). Note that

during all non-burst read operations, the PCnet-PCI

controller will always activate all byte enables, even

though some byte lanes may not contain valid data as

indicated by a buffer pointer value. In such instances,

the PCnet-PCI controller will internally discard un-

needed bytes.

Figure 2 shows a typical non-burst read access. The

PCnet-PCI controller asserts

IRDY at clock 5 immedi-

ately after the address phase and starts sampling

DEVSEL. The target extends the cycle by asserting

DEVSEL not until clock 6. Additionally, the target inserts

one wait state by asserting its ready (

TRDY) at clock 8.

18220C-4

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

12345678

0000

PAR

DATA

DEVSEL is sampled by the PCnet-PCI controller.

ADDR

0110

Figure 2. Non-Burst Read Cycle With Wait States

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