AM79C970 datasheet(34/168 Pages) AMD

34 / 168 page

P R E L I M I N A R Y

AMD

1-901

Am79C970

Descriptor DMA Transfers

PCnet-PCI microcode will determine when a descriptor

access is required. A descriptor DMA read will consist of

two DWORD (double-word) transfers. A descriptor

DMA write will consist of one or two DWORD transfers.

(The transfers within a descriptor DMA transfer master-

ship period will always be of the same type (either all

read or all write)).

If buffer chaining is used, writes to the descriptors of all

intermediate buffers consist of only one DWORD to

return OWNership of the buffer to the system. On all sin-

gle buffer transmit or receive descriptors, as well as on

the last buffer in chain, writes to the descriptor consist of

two DWORDs. The first DWORD containing status in-

formation. The second DWORD containing additional

status and the OWNership bit (i.e. MD1[31]).

The transfers will be addressed as specified in tables 1

and 2.

Table 1. Bus Master Reads of Descriptors

Address

LANCE/

Address

LANCE/

Sequence

PCnet-ISA

PCnet-PCI

Sequence

PCnet-ISA

PCnet-PCI

AD[7:0]*

Item Accessed

AD[7:0]*

Item Accessed

MD1[15:0],

MD1[31:24],

MD1[15:8],

MD1[31:0]

MD0[15:0]

MD0[23:0]

MD2[15:0]

MD3[15:0],

MD2[15:0],

MD1[7:0],

MD0[31:0]

MD2[15:0]

MD1[15:0]

MD0[15:0]

Bus Break

16-Bit Software Mode

32-Bit Software Mode

Table 2. Bus Master Writes to Descriptors

Address

LANCE/

Address

LANCE/

Sequence

PCnet-ISA

PCnet-PCI

Sequence

PCnet-ISA

PCnet-PCI

AD[7:0]*

Item Accessed

AD[7:0]*

Item Accessed

MD3[15:0],

MD2[15:0],

MD3[15:0]

MD2[31:0]

MD2[15:0]

MD1[15:0]

MD1[15:0],

MD1[31:24],

MD1[15:8],

MD1[31:0]

MD0[15:0]

MD0[23:0]

MD2[15:0]

Bus Break

16-Bit Software Mode

32-Bit Software Mode

* Address values for AD[31:08] are constant throughout any single descriptor DMA transfer. AD[1:0] must be set to ZERO in the

descriptor base address.

During descriptor read accesses, the byte enable sig-

nals will indicate that all byte lanes are active. Should

some of the bytes not be needed, then the PCnet-PCI

controller will internally discard the extraneous informa-

tion that was gathered during such a read. During write

accesses, only the bytes which need to be written are

enabled, by activating the corresponding byte en-

able pins.

The only significant differences between descriptor

DMA transfers and initialization DMA transfers are that

the addresses of the accesses follow different ordering.

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