AM79C970 datasheet(93/168 Pages) AMD

93 / 168 page

AMD

P R E L I M I N A R Y

1-960

Am79C970

the PCnet-PCI controller initial-

zation routine.

Read

accessible

only

when

STOP bit is set. Write operations

have no effect and should not be

performed. RLEN is only defined

after initialization. These bits are

unaffected by H_RESET, S_RE-

SET or STOP.

7–0

RES

Reserved locations. Read as

ZERO. Write operations should

not be performed.

CSR8: Logical Address Filter, LADRF[15:0]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 LADRF[15:0]

Logical

Address

Filter,

LADRF[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct I/O write has been per-

formed on this register.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR9: Logical Address Filter LADRF[31:16]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 LADRF[31:16] Logical

Address

Filter,

LADRF[31:16]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct I/O write

has been performed on this

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR10: Logical Address Filter, LADRF[47:32]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 LADRF[47:32] Logical

Address

Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct I/O write

has been performed on this

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR11: Logical Address Filter, LADRF[63:48]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 LADRF[63:48] Logical

Address

Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct I/O write

has been performed on this

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR12: Physical Address Register, PADR[15:0]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 PADR[15:0]

Physical

Address

PADR[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct I/O write has been per-

formed on this register.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR13: Physical Address Register, PADR[31:16]

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 PADR[31:16]

Physical

Address

PADR[31:16]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct I/O write has been per-

formed on this register.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

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