AM79C970 datasheet(121/168 Pages) AMD

121 / 168 page

AMD

P R E L I M I N A R Y

1-988

Am79C970

7–0 SWSTYLE

Software

Style

The

value in this register determines

the style of I/O resources that

shall be used by the PCnet-PCI

controller. The Software Style

selection will affect the interpre-

tation of a few bits within the CSR

space and the width of the de-

scriptors and initialization block.

Specifically:

Table 12. SWSTYLE Values

SWSTYLE

Style

CSR-

Altered Bit

[7:0]

Name

PCNET SSIZE32 Interpretations

00h

LANCE/

ALL CSR4 bits will

PCnet-

function as defined in

ISA

the CSR4 section.

TMD1[29] functions as

ADD_FCS

01h

ILACC

CSR4[9:8], CSR4[5:4]

and CSR4[1:0] will

have no function, but

will be writeable and

readable.

CSR4[15:10], CSR4[7:6]

and CSR4[3:2] will

function as defined in the

CSR4 section.

TMD1[29] becomes

NO_FCS.

02h

PCnet-

ALL CSR4 bits will

PCI

function as defined in

the CSR4 section.

TMD1[29] functions as

ADD_FCS

All other

Res.

Undef.

combs.

All PCnet-PCI controller CSR

bits and BCR bits and all descrip-

tor, buffer and initialization block

entries not cited in the table

above are unaffected by the Soft-

ware Style selection and are

therefore always fully functional

as specified in the CSR and BCR

sections.

Read/write accessible only when

STOP bit is set.

The SWSTLYE register will con-

tain the value 00h following

H_RESET or S_RESET and will

be unaffected by STOP.

BCR21: Interrupt Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 INTCON

Reserved locations. Writes to

this register will have no effect on

the operation of the PCnet-PCI

controller.

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