WM9713 datasheet(33/111 Pages) WOLFSON

33 / 111 page

Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

15:14

ALCSEL

(OFF)

ALC function select

00 = ALC off (PGA gain set by register)

01 = Right channel only

10 = Left channel only

11 = Stereo (PGA registers unused)

13:11

MAXGAIN

111

(+30dB)

PGA gain limit for ALC

111 = +30dB

110 = +24dB

….(6dB steps)

001 = -6dB

000 = -12dB

10:9

ZCTIMEOUT

Programmable zero cross timeout (delay

for 12.288MHz BITCLK):

11: 2^17 * tbitclk (10.67 ms)

10: 2^16 * tbitclk (5.33 ms)

01: 2^15 * tbitclk (2.67 ms)

00: 2^14 * tbitclk (1.33 ms)

62h

ALC / Noise

Gate Control

ALCZC

ALC Zero Cross enable (overrides ZC

bit in register 12h)

0: PGA Gain changes immediately

1: PGA Gain changes when signal is

zero or after time-out

15:12

ALCL

1011

(-12dB)

ALC target – sets signal level at ADC

input

0000 = -28.5dB FS

0001 = -27.0dB FS

… (1.5dB steps)

1110 = -7.5dB FS

1111 = -6dB FS

11:8

HLD

0000

(0ms)

ALC hold time before gain is increased.

0000 = 0ms

0001 = 2.67ms

0010 = 5.33ms

… (time doubles with every step)

1111 = 43.691s

7:4

DCY

0011

(192ms)

ALC decay (gain ramp-up) time

0000 = 24ms

0001 = 48ms

0010 = 96ms

… (time doubles with every step)

1010 or higher = 24.58s

60h

ALC Control

3:0

ATK

0010

(24ms)

ALC attack (gain ramp-down) time

0000 = 6ms

0001 = 12ms

0010 = 24ms

… (time doubles with every step)

1010 or higher = 6.14s

Table 13 ALC Control

MAXIMUM GAIN

The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the

control of the ALC. This has no effect on the PGA when ALC is not enabled.

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