S2-LP datasheet(50/90 Pages) STMICROELECTRONICS

50 / 90 page

Operating modes

S2-LP

50/90

DocID029944 Rev 1

Command

code

Command name

State for

execution

Description

0x72

FLUSHTXFIFO

All

Clean the TX FIFO

0x73

SEQUENCE_UPDA

ANY

Reload the packet sequence counter

with the value stored in register

6.2

State transaction response time

Table 47: Response time

Initial state

Final state

Response time [µs]

SHUTDOWN

READY

500

READY

STANDBY/ SLEEP

0.3

READY

LOCK with no VCO calibration

READY

LOCK with VCO calibration

RX/TX

READY

STANDBY/SLEEP

READY

The transition time enables the S2-LP for frequency hopping operation due to its

reduced response time and very quick programming synthesizer. The response

time depends on frequency of the clock in digital domain, from 24 MHz to 26 MHz.

6.3

Sleep states

S2-LP provides 2 SLEEP states:



SLEEP without FIFO retention (SLEEP_A): in this low power state, the device keeps

all the register values but not the TX and RX FIFOs. This is the device default SLEEP

state.



SLEEP with FIFO retention (SLEEP_B): in this low power state, the device keeps the

content of the registers and the two FIFOs.

The responsibility of the SLEEP type to be used is demanded to the user. To select the

SLEEP mode, the bit SLEEP_MODE_SEL (register 0x79) can be used. If this bit is set to 0,

SLEEP_A will be used each time the device will enter in SLEEP (by SPI command, LDC

flow or CSMA in non-persistent mode). If it is 1, SLEEP_B will be used instead.

The usage of SLEEP_B mode is mandatory in the configuration like CSMA and LDC in Tx.

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