LIS2HH12 datasheet(13/47 Pages) STMICROELECTRONICS

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DocID025344 Rev 5

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LIS2HH12

Mechanical and electrical specifications

2.4.2

I2C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Figure 4. I2C slave timing diagram

Note:

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Table 7. I2C slave timing values

Symbol

Parameter

I2C standard mode (1)

I2C fast mode (1)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

100

400

kHz

tw(SCLL)

SCL clock low time

4.7

1.3

μs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0.01

3.45

0.01

0.9

μs

th(ST)

START condition hold time

0.6

μs

tsu(SR)

Repeated START condition

setup time

4.7

0.6

tsu(SP)

STOP condition setup time

0.6

tw(SP:SR)

Bus free time between STOP

and START condition

4.7

1.3

1. Data based on standard I2C protocol requirement, not tested in production

SDA

SCL

tsu(SP)

tw(SCLL)

tsu(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tw(SP:SR)

START

REPEATED

START

STOP

START

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