LIS2HH12 datasheet(38/47 Pages) STMICROELECTRONICS

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LIS2HH12

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DocID025344 Rev 5

8.16

FIFO_CTRL (2Eh)

FIFO control register (r/w)

Table 41. FIFO control register

The FIFO trigger is the IG_SRC1 (31h) event. (Refer to IG_SRC1 (31h)).

8.17

FIFO_SRC (2Fh)

FIFO status control register (r)

Table 44. FIFO status register

Table 45. FIFO status register description

FMODE2

FMODE1

FMODE0

FTH4

FTH3

FTH2

FTH1

FTH0

Table 42. FIFO control register description

FMODE [2:0]

FIFO mode selection bits. Default: 000. For further details refer to table below

FTH [4:0]

FIFO threshold. Default: 00000. It is the FIFO depth if the STOP_FTH bit in the

CTRL3 (22h) register is set to ‘1’.

Table 43. FIFO mode selection

FMODE2

FMODE1

FMODE0

Mode

Bypass mode. FIFO turned off

FIFO mode. Stops collecting data when FIFO is full.

Stream mode. If the FIFO is full, the new sample overwrites

the older one

Stream mode until trigger is deasserted, then FIFO mode

Bypass mode until trigger is deasserted, then Stream mode

Not used

Bypass mode until trigger is deasserted, then FIFO mode

FTH

OVR

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

FTH

FIFO threshold status.

0: FIFO filling is lower than FTH level; 1: FIFO filling is equal to or higher than

threshold level

OVR

Overrun bit status. 0: FIFO is not completely filled; 1: FIFO is completely filled

EMPTY

FIFO empty bit.

0: FIFO not empty; 1: FIFO empty)

FSS [4:0]

FIFO stored data level

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