PC97307 datasheet(175/218 Pages) NSC

175 / 218 page

175

Power Management (Logical Device 8)

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9.2.7

Power Management Control 3 Register (PMC3),

Index 04h

Hardware resets this register to 0Eh.

FIGURE 9-7. PMC3 Register Bitmap

Bit 0 - Reserved

This bit is reserved.

Bit 1 - Parallel Port Clock Enable

This bit is ANDed with bit 1 of the SuperI/O Parallel Port

Configuration register at index F0h of logical device 4. If

either bit is cleared to 0, the clock is disabled. Both bits

must be set to 1 to enable the clock.

0 - The clock is disabled.

1 - If bit 1 of the SuperI/O Parallel Port Conﬁguration

Bit 2 - UART2 Clock Enable

This bit is ANDed with bit 1 of the SuperI/O UART2 Con-

figuration register at index F0h of logical device 5. If ei-

ther bit is cleared to 0, the clock is disabled. Both bits

must be set to 1 to enable the clock.

0 - The clock is disabled.

1 - If bit 1 of the SuperI/O UART2 Conﬁguration regis-

ter is set to 1, the clock is enabled. (Default)

Bit 3 - UART1 Clock Enable

This bit is ANDed with bit 1 of the SuperI/O UART1 Con-

figuration register at index F0h of logical device 6. If, ei-

ther bit is cleared to 0, the clock is disabled. Both bits

must be set to 1 to enable the clock.

0 - The clock is disabled.

1 - If bit 1 of the SuperI/O UART1 Conﬁguration regis-

ter is set to 1, the clock is enabled. (Default)

Bits 5,4 - Reserved

These bits are reserved.

Bit 6 - UART2 Busy

When set to 1,this read-only bit indicates the UART2 is

busy. It is also accessed via the SuperI/O UART2 Con-

figuration register at index F0h of logical device 5. See

Section 2.8 on page 38.

UART1 Clock Enable

76543210

Reset

Required

Index 04h

Power Management

Control 3 Register

Reserved

UART1 busy

UART2 Busy

UART2 Clock Enable

Parallel Port Clock Enable

(PMC3)

Bit 7 - UART1 Busy

When set to 1,this read-only bit indicates the UART1 is

busy. It is also accessed via the SuperI/O UART2 Configu-

ration register at index F0h of logical device 6. See Section

2.9.1 on page 38.

9.2.8

Watchdog Time-Out (WDTO) Register,

Index 05h

This read/write register specifies the WATCHDOG time-out

period programmed by the user. It does not reflect the cur-

rent count while a countdown is in progress. The time-out

period may be from 1 to 255 minutes.

This register is cleared to 00h after reset. This register is

also reset to zero and disabled when the Power Manage-

ment device is activated.

See “The WATCHDOG Feature” on page 172 for more in-

formation.

FIGURE 9-8. WDTO Register Bitmap

Bits 7-0 - Programmed Time-Out Period

These bits contain the programmed time-out period for

the WATCHDOG timer. They do not reflect the current

count while countdown is in progress.

Writing the value 00h resets the timer and deactivates

the WDO signal. Hardware reset clears the register to

00h, and deactivates the WATCHDOG timer function

and WDO. Software reset deactivates power manage-

ment (logical device 8) and resets the WATCHDOG tim-

er.

Values between 1 and 255 specify the countdown peri-

od, with one minute for each decrement.

When the timer reaches 00h, the WDO signal is enabled

(active low).

Writing a non-zero value to these bits resets the WDO

signal to 1 (inactive high).

9.2.9

WATCHDOG Configuration Register (WDCF),

Index 06h

This register enables or masks the trigger events that re-

start the WATCHDOG timer.

When an enabled trigger event occurs, the programmed

time-out value (the value in the WDTO register) is reloaded

into the WATCHDOG timer. The WATCHDOG timer can

reach zero and activate WDO only if no trigger event occurs

for an entire time-out period.

Trigger events are not affected by the polarity or type of the

module interrupt.

76543210

Reset

Required

WATCHDOG Time-Out

Index 05h

Programmed Time-Out Period

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