PC97307 datasheet(176/218 Pages) NSC

176 / 218 page

176

Power Management (Logical Device 8)

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Upon reset and upon activation of the power management

device, all trigger events are disabled, i.e., bits are cleared

to zero.

See “The WATCHDOG Feature” on page 172 for more in-

formation.

FIGURE 9-9. WDCF Register Bitmap

Bit 0 - KBC IRQ Trigger Enable

This bit enables the IRQ assigned to the KBC to trigger

reloading of the WATCHDOG timer.

Reset clears this bit to 0.

0 - KBC IRQ trigger disabled. (Default)

1 - An active KBC IRQ signal triggers reloading of the

WATCHDOG timer.

Bit 1 - Mouse IRQ Trigger Enable

This bit enables the IRQ assigned to the mouse to trig-

ger reloading of the WATCHDOG timer.

Reset clears this bit to 0.

0 - Mouse IRQ trigger disabled. (Default)

1 - An active mouse IRQ signal triggers reloading of

the WATCHDOG timer.

Bit 2 - UART1 IRQ Trigger Enable

This bit enables the IRQ assigned to UART1 to trigger

reloading of the WATCHDOG timer.

Reset clears this bit to 0.

0 - UART1 IRQ trigger disabled. (Default)

1 - An active UART1 IRQ signal triggers reloading of

the WATCHDOG timer.

Bit 3 - UART2 IRQ Trigger Enable

This bit enables the IRQ assigned to UART2 to trigger

reloading of the WATCHDOG timer.

Reset clears this bit to 0.

0 - UART2 IRQ trigger disabled. (Default)

1 - An active UART2 IRQ signal triggers reloading of

the WATCHDOG timer.

Bits 7-4 - Reserved

Reserved

76543210

Reset

Required

WATCHDOG Configuration

Index 06h

Mouse IRQ Trigger Enable

UART1 IRQ Trigger Enable

UART2 IRQ Trigger Enable

KBC IRQ Trigger Enable

Reserved

9.2.10

WATCHDOG Status Register (WDST),

Index 07h

Bit 1 of this register contains the value of the WDO signal,

for monitoring by software.

On reset or on PM logical device activation this register is

initialized to 01h.

See “The WATCHDOG Feature” on page 172 for more in-

formation.

FIGURE 9-10. WDST Register Bitmap

Bit 0 - WDO Value

This read-only bit reflects the value of WDO. It is initial-

ized to 1 by a hardware reset.

This bit reflects the status of the WDO signal, even if

WDO is not configured for output by bit 6 of SuperI/O

Configuration register 2, in which case the pin is used

for GPIO17.

0 - WDO is active.

1 - WDO is not active. (Default)

Bits 7-1 - Reserved

These bits are reserved.

Reserved

76543210

Reset

Required

WATCHDOG Status

Index 07h

WDO Value

PC97307 데이터시트(PDF) 176 Page - National Semiconductor (TI)

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