PC87366 datasheet(114/240 Pages) NSC

114 / 240 page

3.0 System Wake-Up Control (SWC) (Continued)

114

www.national.com

Event Conﬁguration

Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predeter-

mined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system

notification.

• Event Type and Polarity - Two trigger types of event detection are supported: edge and level. An edge event may be

detected upon a source pin transition either from high to low or low to high. A level event may be detected when the

source pin is in active level. The trigger type is determined by Event Type (bit 4). The direction of the transition (for edge)

or the polarity of the active level (for level) is determined by Event Polarity (bit 5).

• Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal

state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure

that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending

indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended

to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event

Debounce Enable (bit 6 of the SBGPIO Pin Configuration register).

3.4.31

Standby GPIO Pin Select Register (SBGPSEL)

This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the

Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset.

When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0. When port 1 is selected, bits 2-0 select be-

tween pins GPOS0 and GPOS1. Pins GPIS2 and GPIS3 are input only and require no configuration.

Location:

Bank 3, Offset 13h

Type:

R/W

Bit

76543210

Name

Reserved

Port Select

Reserved

Pin Select

Reset

00000000

Bit

Description

7-5

Reserved

Port Select. This bit selects the GPIO port to be conﬁgured.

0: Port 0 (default)

1: Port 1

Reserved

2-0

Pin Select. These bits select the GPIO pin to be conﬁgured in the selected port.

000, 001, ... 111:The binary value of the pin number, 0, 1, ... 7 respectively (default=0)

PC87366 데이터시트(PDF) 114 Page - National Semiconductor (TI)

PC87366 데이터시트(HTML) 114 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL