PC87366 datasheet(115/240 Pages) NSC

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3.0 System Wake-Up Control (SWC) (Continued)

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3.4.32

Standby GPIO Pin Configuration Register (SBGPCFG)

This is a group of twelve configuration registers. Eight are identical for GPIOE and GPIE, two are identical for GPOS, and .

two are identical for GPIS. Each GPIOE/GPIE register is associated with one GPIOE/GPIE pin, and each GPOS and GPIS

based on the Standby GPIO Pin Select (SBGPSEL) register that functions as an index register, and the specific Standby

GPIO Pin Configuration register that reflects the configuration of the currently selected pin.

Bits 0-3 are applicable only for pins GPIOE0-5 and GPOS0,1. Bits 4-6 are applicable for all GPIOE/GPIE pins.

Location:

Bank 3, Offset 14h

Type:

R/W (bit 3 is set only)

For GPIOE and GPIE:

For GPOS:

For GPIS:

Bit

76543210

Name

Reserved

Event

Debounce

Enable

Event

Polarity

Event Type

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

01000100

Bit

76543210

Name

Reserved

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

00000101

Bit

76543210

Name

Reserved

Reset

00000000

Bit

Description

Reserved (for GPOS and GPIS, bits 7-4 and 7-0 are reserved, respectively)

Event Debounce Enable

0: Disabled

1: Enabled (default)

Event Polarity. This bit deﬁnes the polarity of the signal that causes a detection of an event from the

corresponding GPIO pin.

0: Falling edge or low level input (default)

1: Rising edge or high level input

Event Type. This bit deﬁnes the signal type that causes a detection of an event from the corresponding GPIO

pin.

0: Edge input (default)

1: Level input

Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by

the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by VSB power-up reset.

0: No effect (default at VSB power-up reset)

1: Direction, output type, pull-up and output value locked

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