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TNETV1644ZDU6 데이터시트(PDF) 229 Page - Texas Instruments

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부품명 TNETV1644ZDU6
상세설명  Digital Media Processor
PDF  306 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV1644ZDU6 데이터시트(HTML) 229 Page - Texas Instruments

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PCLK
(Positive Edge Clocking)
9
PCLK
(Negative Edge Clocking)
10
VCTL(A)
A. VCTL = HSYNC and VSYNC
VPBECLK
27
28
33
34
35
36
LCD_FIELD
TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-43. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK(1) (see
Figure 6-24)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
UNIT
MIN
MAX
9
tsu(VCTLV-PCLK)
Setup time, VCTL valid before PCLK edge
3
ns
10
th(PCLK-VCTLV)
Hold time, VCTL valid after PCLK edge
1
ns
27
tsu(VCTLV-VPBECLK)
Setup time, VCTL valid before VPBECLK rising edge
3
ns
28
th(VPBECLK-VCTLV)
Hold time, VCTL valid after VPBECLK rising edge
1
ns
33
tsu(FIELD-PCLK)
Setup time, LCD_FIELD valid before PCLK edge
5P(2)
ns
34
th(PCLK-FIELD)
Hold time, LCD_FIELD valid after PCLK edge
5P(2)
ns
35
tsu(FIELD-VPBECLK)
Setup time, LCD_FIELD valid before VPBECLK edge
5P(2)
ns
36
th(VPBECLK-FIELD)
Hold time, LCD_FIELD valid after VPBECLK edge
5P(2)
ns
(1)
PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
(2)
P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.
Figure 6-24. VPBE Input Timing With Respect to PCLK and VPBECLK
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
229



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