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TNETV1644ZDU6 데이터시트(PDF) 231 Page - Texas Instruments

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부품명 TNETV1644ZDU6
상세설명  Digital Media Processor
PDF  306 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV1644ZDU6 데이터시트(HTML) 231 Page - Texas Instruments

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VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
17
VCTL(B)
VDATA(C)
18
19
22
21
23
24
25
26
VCLKIN(A)
A. VCLKIN = PCLK or VPBECLK
B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
20
20
TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-45. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK(1)(2)(3) (see Figure 6-26)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
UNIT
MIN
MAX
17
tc(VCLK)
Cycle time, VCLK
13.33
160
ns
18
tw(VCLKH)
Pulse duration, VCLK high
0.4C
ns
19
tw(VCLKL)
Pulse duration, VCLK low
0.4C
ns
20
tt(VCLK)
Transition time, VCLK
7
ns
21
td(VCLKINH-VCLKH)
Delay time, VCLKIN high to VCLK high
1
9
ns
22
td(VCLKINL-VCLKL)
Delay time, VCLKIN low to VCLK low
1
9
ns
23
td(VCLK-VCTLV)
Delay time, VCLK edge to VCTL valid
9
ns
24
td(VCLK-VCTLIV)
Delay time, VCLK edge to VCTL invalid
0.6
ns
25
td(VCLK-VDATAV)
Delay time, VCLK edge to VDATA valid
9
ns
26
td(VCLK-VDATAIV)
Delay time, VCLK edge to VDATA invalid
0.6
ns
(1)
The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2)
VCLKIN = PCLK or VPBECLK
(3)
C = VCLK period in ns.
Figure 6-26. VPBE Control and Data Output Timing With Respect to VCLK
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
231



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