A5974D datasheet(10/46 Pages) STMICROELECTRONICS

10 / 46 page

Functional description

A5974D

10/46

DocID018774 Rev 2

5.2

Voltages monitor

An internal block continuously senses the VCC, Vref and Vbg. If the voltages go higher than

their thresholds, the regulator begins operating. There is also a hysteresis on the VCC

(UVLO).

Figure 4. Internal circuit

5.3

Oscillator and synchronization

Figure 5 shows the block diagram of the oscillator circuit.

The clock generator provides the switching frequency of the device, which is internally fixed

at 250 kHz. The frequency shifter block acts to reduce the switching frequency in case of

strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry

and is the input of the ramp generator and synchronizer blocks.

The ramp generator circuit provides the sawtooth signal, used for PWM control and the

internal voltage feed-forward, while the synchronizer circuit generates the synchronization

signal. The device also has a synchronization pin which can work both as master and slave.

Beating frequency noise is an issue when more than one voltage rail is on the same board.

A simple way to avoid this issue is to operate all the regulators at the same switching

frequency.

The synchronization feature of a set of the A5974D is simply get connecting together their

SYNCH pin. The device with highest switching frequency will be the MASTER and it

provides the synchronization signal to the others. Therefore the SYNCH is an I/O pin to

deliver or recognize a frequency signal. The synchronization circuitry is powered by the

internal reference (VREF) so a small filtering capacitor (100 nF) connected between VREF

pin and the signal ground of the master device is suggested for its proper operation.

However when a set of synchronized devices populates a board it is not possible to know in

advance the one working as a master, so the filtering capacitors have to be designed for

whole set of devices.

When one or more devices are synchronized to an external signal, its amplitude have to be

in comply with specifications given in Table 4 on page 6. The frequency of the

synchronization signal must be, at a minimum, higher than the maximum guaranteed natural

switching frequency of the device (275 kHz, see Table 4) while the duty cycle of the

synchronization signal can vary from approximately 10% to 90%. The small capacitor under

the VREF pin is required for this operation.

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