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A5974D 데이터시트(PDF) 11 Page - STMicroelectronics |
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A5974D 데이터시트(HTML) 11 Page - STMicroelectronics |
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11 / 46 page ![]() DocID018774 Rev 2 11/46 A5974D Functional description 46 Figure 5. Oscillator circuit block diagram Figure 6. Synchronization example 5.4 Current protection The A5974D device features two types of current limit protection: pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time necessary to sense the current in order to avoid a false overcurrent signal is too short to obtain a sufficiently low duty cycle at 250 kHz (see Section 8.5 on page 31), the output current in strong overcurrent or short-circuit conditions could be not properly limited. For this reason OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH OUT GND COMP FB SS/INH A5973D SYNCH A5974D A5974D A5974D A5974D |
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